DC to DC converter with overvoltage protection circuit

ABSTRACT

An overvoltage protection circuit limits the output voltage of a DC to DC converter to a maximum desired output voltage. An output voltage sensing circuit includes a semiconductor device such as a sidac having a normal resistive region of operation as well as a negative resistance region of operation which begins at a breakover voltage and extends into a foldback region. One terminal of the sidac is coupled to sense the converter output voltage while the second terminal opposite end of the sidac is coupled to a biasing device in the form of a resistor which generates an overvoltage signal when the sidac conducts current. The overvoltage signal from the biasing resistor is coupled to a converter switching transistor disabling circuit which reduces the converter output voltage to a level below the maximum desired output voltage in response to the overvoltage signal.

This application is a continuation-in-part of allowed U.S. Pat. Application Ser. No. 794,415, filed on 11/4/85, now U.S. Pat. No. 4,682,081. The disclosure of that patent is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to power supplies, and more particularly to DC to DC converter circuits commonly utilized to energize gaseous discharge tubes in the form of strobe flash lamps.

2. Description of the Prior Art

Prior art DC to DC converter circuits of the type utilized to energize strobe flash lamps are typically designed to operate at a single input voltage. For vehicular applications, such power supplies are typically designed to operate at either one of the following input voltage levels: twelve volts DC, twenty-four volts DC, thirty-six volts DC or forty-eight volts DC. A wholesaler or distributor who supplies vehicular-mounted strobe power supplies must normally carry an inventory of strobe power supply circuits for each of these four distinct and previously incompatible power supply input voltage ratings.

Strobe power supplies for vehicular applications typically include DC to DC converter circuits using a coupled inductor having primary and feedback windings which are controlled by a switching transistor coupled in series with the current flow path of the primary winding. In all cases, it is necessary to miniaturize such power supply circuits to the maximum extent possible to render them compatible with vehicular installations. In addition, the efficiency of these power supply circuits must be as high as possible due to the relatively limited electrical power generating capacity of the vehicles on which such power supply circuits are mounted. As is always the case, the cost of such circuits must be kept as low as possible and the reliability of these circuits which are exposed to extreme environmental conditions must be as high as possible.

From the customer and distributor standpoint, this prior art solution to the numerous problems addressed above has been begrudgingly accepted, but the additional cost and inconvenience caused by the requirement for stocking and using four different input voltage capacity power supplies has long been recognized.

SUMMARY OF THE INVENTION

It is therefore a primary object of the present invention to provide a drive current regulator circuit for a variable input voltage DC to DC converter for supplying a constant base drive current to the converter circuit switching transistor which does not vary in response to substantial changes in the converter DC input voltage.

Another object of the present invention is to provide a drive current regulator circuit for a variable input voltage DC to DC converter which couples a constant current source to the feedback winding of the converter coupled inductor to provide a constant base drive current to the converter switching transistor regardless of feedback winding voltage or the converter DC input voltage.

Another object of the present invention is to provide a drive current regulator circuit for a variable input voltage DC to DC converter which can provide a constant, optimum level base drive current to the converter switching transistor to maintain optimum, highest efficiency performance of the converter circuit where circuit performance is essentially insensitive to substantial variations in the converter DC input voltage.

Another object of the present invention is to provide an afterglow prevention circuit for a DC to DC converter which prevents strobe flash lamp afterglow caused by the transfer of high level converter DC input voltages to the flash lamp during the time interval immediately after the converter energy storage capacitor has completed its discharge cycle through the strobe flash lamp to thereby prevent afterglow.

Another object of the present invention is to provide an afterglow prevention circuit for a DC to DC converter which utilizes a variable impedance device in the form of a capacitor placed in series between the converter switching transistor and the converter energy storage capacitor to provide a low impedance path between the primary winding of the converter coupled inductor and the energy storage capacitor when the converter operates at high frequencies and to provide a high impedance path between the primary winding of the coupled inductor and the energy storage capacitor when the converter operates at low frequencies.

Another object of the present invention is to provide an afterglow prevention circuit for a DC to DC converter which can readily be adapted to function in connection with prior art DC to DC converter circuits to totally eliminate afterglow problems caused by power supply input voltage feed through to an ionized strobe flash lamp at the end of the energy storage capacitor discharge cycle.

Another object of the present invention is to provide an overvoltage protection circuit for a DC to DC converter which limits the maximum converter output voltage without affecting the operating efficiency of the converter circuit.

Another object of the present invention is to provide an overvoltage protection circuit for a DC to DC converter which can be added to prior art DC to DC converter circuits without modification of the existing circuitry and with the addition of only a limited number of additional circuit elements.

Another object of the present invention is to provide an overvoltage protection circuit for a DC to DC converter which utilizes a semiconductor device in the form of a sidac having a breakover voltage and a negative resistance region.

Another object of the present invention is to provide an overvoltage protection circuit for a DC to DC converter which completely terminates the operation of the converter switching transistor for a predetermined time period enabling the energy storage capacitor output voltage to be decreased to a level below the maximum desired output voltage before the converter switching transistor is once again enabled to commence normal operation.

Briefly, stated, and in accord with one embodiment of the invention, a DC to DC converter includes an overvoltage protection circuit which limits the converter output voltage to a capacitive load to a maximum desired output voltage. The overvoltage protection circuit includes overvoltage sensing means including semiconductor means and semiconductor biasing means. The semiconductor means typically takes the form of a sidac or equivalent semiconductor device which includes a resistive region of operation and a negative resistance of operation beginning at a breakover voltage and extending into a foldback region. The semiconductor means includes a first terminal which is coupled to sense the converter output voltage and a second terminal. The semiconductor means commences to conduct current at the breakover voltage which is selected to correspond to the maximum desired converter output voltage. The biasing means includes an input terminal which is coupled to the second terminal of the semiconductor means as well as an output terminal. The biasing means generates an overvoltage signal when the semiconductor means conducts current. Power supply disabling means is coupled to the second terminal of the biasing means and to the switching transistor of the converter circuit. The power supply disabling means is responsive to the overvoltage signal from the biasing means and serves to reduce the power supply output voltage to a level below the maximum desired output voltage.

DESCRIPTION OF THE DRAWINGS

The invention is pointed out with particularly in the appended claims. However, other objects and advantages together with the operation of the invention may be better understood by reference to the following detailed description taken in connection with the following illustrations, wherein:

FIG. 1 is a schematic diagram of a first preferred embodiment of the invention including the drive current regulator circuit, the afterglow prevention circuit and the overvoltage protection circuit aspects of the present invention.

FIG. 2 is a partial schematic diagram depicting an alternative preferred embodiment of the afterglow prevention circuit of the present invention which operates in combination with the overvoltage protection circuit of the present invention to maintain a constant magnitude energy discharge into the strobe flash lamp regardless of variations in the DC to DC converter circuit input voltage.

FIG. 3 is a timing diagram showing the relationship to time of the switching transistor operating frequency with respect to the energy storage capacitor voltage as well as the charge and discharge cycles of the converter energy storage capacitor.

FIG. 4 is a partial schematic diagram of the FIG. 1 DC to DC converter circuit particularly illustrating the manner in which the variable impedance means of the present invention blocks current flow caused by the converter DC input voltage into the strobe flash lamp when it is in the ionized state.

FIGS. 5A, 5B and 5C represent voltage versus current plots for negative resistance devices in the form f a sidac, a diac and a silicon bilateral switch which are capable of functioning in the overvoltage protection circuit of the present invention.

FIG. 6 represents a partial schematic diagram of a prior art resistive biasing circuit for a DC to DC converter.

FIG. 7A graphically illustrates variations in feedback winding voltage with respect to variations in input voltage. FIG. 7B illustrates variations in the FIG. 6 switching transistor base current in response to variations in the converter input voltage. FIG. 7C illustrates the absence of variations of the switching transistor base drive current with respect to input voltage variations for the drive current regulator circuit of the present invention.

FIG. 8 is a partial schematic diagram illustrating the use of a constant current diode in the drive regulator circuit of the present invention in place of the more complicated constant current source drive regulator circuit depicted in the FIG. 1 schematic diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In order to better illustrate the advantages of the invention and its contributions to the art, a preferred hardware embodiment of the invention will now be described in detail.

Referring now to FIG. 1, the DC to DC converter of the present invention includes a coupled inductor having a primary winding 10 and a feedback winding 12. The collector terminal of a switching transistor 14 is coupled to primary winding 10 while the emitter of that transistor is coupled to ground through emitter load resistor 16.

An input voltage residing generally between the range of twelve to forty-eight volts DC is coupled across voltage input terminal 18 and ground terminal 20. A starting base bias current is provided to the base terminal of switching transistor 14 by current flow through resistor 22. This starting bias current turns switching transistor 14 on and causes the current through transistor 14 to increase. When the current level through switching transistor 14 reaches a predetermined maximum value, the voltage on emitter resistor 16 activates power supply disabling means which includes transistor 24 and diode 26. The value of emitter resistor 16 is selected so hat diode 26 commences conducting current at exactly the point when the collector current of switching transistor 14 reaches the maximum desired value. The flow of current through diode 26 indicated by current flow arrow 28 turns on transistor 24 and shunts all base drive current to ground as indicated by current flow arrow 30.

As current initially begins to flow through primary winding 10 and switching transistor 14, a positive voltage is generated across feedback winding 12 as indicated by the "+" sign depicted in FIG. 1. This positive voltage is coupled to the input terminal of drive regulator means 32 which includes a constant voltage biasing network including zener diode 34 and resistor 36. The configuration of the coupled inductor including primary winding 10 and feedback winding 12, the turns ratios of these windings and related transformer design parameters are configured so that the positive voltage generated by feedback winding 12 immediately causes zener diode 34 to break down and begin conducting current as indicated by current flow arrow 38. This constant voltage biasing network produces a constant bias voltage which does not vary in response to changes in the converter input voltage within the design parameters of twelve to forty-eight volts DC. This constant bias voltage point is directly coupled to the base of constant current transistor 40. Transistor 40 immediately begins generating a constant current output which is directed through diode 42 and into the base terminal of switching transistor 14 as indicated by current flow arrow 44. The arrival of this base drive current on the base terminal of switching transistor 14 maintains transistor 14 in the "on" or conductive state until transistor 24 of the power supply disabling means is once again activated to shunt the base drive current to ground in response to the bias voltage produced across emitter resistor 16.

The magnitude of the base drive current produced by drive regulator means 32 can be adjusted between minimum and maximum allowable levels or to an optimum base drive level by adjusting potentiometer 46.

Referring now to FIG. 7, FIG. 7A illustrates the changes in feedback winding voltage produced in response to changes in the converter input voltage and illustrates the manner in which the feedback winding voltage increases in response to increases in the converter input voltage.

FIG. 7B illustrates the manner in which the base drive current 44 generated by the FIG. 6 prior art resistive drive regulator circuit varies linearly in response to changes in the converter input voltage. For a comparatively low input voltage such as twelve volts, FIG. 7B indicates that the base drive current produced by the prior art FIG. 6 circuit fails to meet the minimum required base drive requirements of switching transistor 14 and would therefore fail to properly operate switching transistor 14. For intermediate level input voltages on the order of twenty-four to thirty-six volts, the base drive current provided by the FIG. 6 prior art circuit varies either below or above the desired optimum base drive current. For higher levels of input voltage on the order of about forty-eight volts DC. FIG. 7B illustrates that the FIG. 6 prior art base drive circuit produces levels of base drive current in excess of the maximum allowable drive level. Excess base drive can cause excessive switching transistor current loads, excessive switching transistor temperatures due to extended transistor storage time and typically results in damage or failure of various system components.

A significant additional problem experienced by the FIG. 6 prior art base drive circuit relates to the power dissipated by base drive resistor 48. With a four fold increase in converter input voltage from twelve to forty-eight volts, the current through resistor 48 increases four fold, but the power dissipated by resistor 48 increases sixteen fold. This creates serious problems relating to requirements for utilizing large, high power dissipation resistors and general circuit heat dissipation problems as well as reduced circuit efficiency resulting from the excessive power dissipation in resistor 48. In addition, as explained above in connection with FIG. 7B, the FIG. 6 resistive base drive regulation circuit is not capable of maintaining an optimum base drive current as the converter input voltage varies.

As indicated by the FIG. 7C plot of input voltage versus base drive current variations achieved by the drive regulator means 32 depicted in FIG. 1, the FIG. 1 circuit is able to provide an absolutely constant level of base drive current regardless of fluctuations in converter input voltage. Appropriate adjustments in potentiometer 46 or an appropriate selection of a fixed resistor value in place of potentiometer 46 can readily cause the FIG. 1 drive regulator means 32 to produce and maintain a constant base drive current for switching transistor 14 to cause that transistor to operate at optimum efficiency regardless of fluctuations of converter input voltage between the design values of from twelve to forty-eight volts DC. With appropriate modifications the circuit element parameters, drive regulator means 32 can readily be adapted to function for various different converter input voltage ranges in a manner well known to those of ordinary skill in the art.

Referring now to FIG. 8, an alternative embodiment of drive regulator means 32 is illustrated in which a constant current diode 50 has been substituted for the related circuit elements depicted in FIG. 1. With some limitations, constant current diode 50 has the capability of functioning to maintain the base drive current constant regardless of fluctuations in the converter input voltage.

Referring now to FIGS. 1 and 4, when switching transistor 14 is switched into the non-conductive state by base drive shunt transistor 24, current flows from primary winding 10 of the coupled inductor through variable impedance means 42 which typically assumes the form of capacitor 52. This current then flows through diode 54 into energy storage means or energy storage capacitor 56. This allowed charging current flow is illustrated in FIGS. 1 and 4 by current flow lines 58.

According to well known transformer operating principles as applied to the converter circuit depicted in FIG. 1, a constant amount of energy is transferred from transformer 10 into capacitor 56 during each time interval that transistor 14 is maintained in the non-conductive state. Referring now also to FIG. 3, when the voltage on capacitor 56 is low as is the case at the beginning of the capacitor charge cycle, a comparatively long period of time is required to transfer a fixed amount of energy or energy from primary winding 10 into capacitor 56. Over a period of charging cycles, the voltage level of capacitor 56 gradually increases as depicted in FIG. 3 until capacitor 56 reaches its peak voltage at the end of a given charging cycle. At this particular point during the charging cycle, only a comparatively short time is required to transfer the fixed amount of energy from primary winding 10 into capacitor 56. The net result of this significant decrease in the time that switching transistor is maintained in the non-conductive state is that the operating frequency of switching transistor 14 varies from a comparatively low frequency on the order of about 5,000 to 10,000 Hertz to a comparatively high frequency on the order of about 40,000 to 50,000 Hertz for the preferred embodiment of the invention depicted in FIG. 1.

Variable impedance means or capacitor 52 is selected to have a comparatively high level impedance at the beginning of a charging cycle which as indicated in FIG. 3 corresponds directly with the end of the flash interval. Similarly, because of the substantial variation in operating frequency between the beginning and end of any charge cycle, variable impedance means or capacitor 52 can easily be selected to have a substantially lower impedance at the high operating frequency end of the charge cycle than was the case with its comparatively low impedance level at the beginning of the charge cycle. Because the voltage on capacitor 56 increases extremely rapidly at the beginning of the charge cycle, any adverse effect of the comparatively high impedance level of capacitor 52 at the beginning of the charge cycle is quickly eliminated.

Variable impedance means 52 was positioned as illustrated in FIGS. 1 and 2 and selected to have the impedance levels described above to prevent afterglow of flash lamp 60.

With prior art converter circuits, input voltages pass through primary winding 10 and are directly coupled to terminal 62 of flash lamp 60 regardless of the operating state of switching transistor 14. When the gaseous interior of flash lamp 60 is initially ionized by trigger circuit 64, the effective impedance of flash lamp 60 drops to an extremely low value on the order of a few Ohms. As illustrated by Fig, 3, upon initial ionization of flash lamp 60 by trigger circuit 64, energy storage means 56 rapidly discharges through flash lamp 60 to a low voltage level determined by the holding current of flash lamp 60. With high level converter input voltages on the order of forty-eight volts DC coupled directly to flash lamp 60, that input voltage by itself is able to maintain flash lamp 60 in the ionized state and creates afterglow illumination during the time interval illustrated in FIG. 3.

With the FIG. 1 circuit, variable impedance means 52 totally blocks the flow of DC current between converter input terminal 18 and flash lamp 60 and totally eliminates the afterglow problem common in prior art units as discussed above.

Referring now to FIG. 4, the dotted line identified by reference number 66 represents the blocked current flow from voltage input terminal 18 to flash lamp 60 achieved by variable impedance means 52. Without such current blocking, high input voltages on terminal 18 which would cause the undesirable afterglow problem described above. In addition, as indicated by reference number 68, energy storage means 56 is permitted to discharge in a normal manner through flash lamp 60 without any interference from variable impedance means 52. Because variable impedance means 52 essentially decouples the potentially high level converter input voltage from flash lamp 60, the termination of current discharge from energy storage means 56 causes the gaseous interior of flash lamp 60 to rapidly deionize which instantaneously terminates flash lamp illumination. As illustrated in FIG. 3, the converter immediately resumes its next capacitor charging cycle at that point in time.

Another design problem encountered and solved by the FIG. 1 circuit relates to problems arising from either burnout or removal of flash lamp 60. Either condition renders flash lamp 60 essentially invisible in the FIG. 1 circuit and the output voltage generated on output voltage conductor 70 begins an uncontrolled increase. If not stopped or otherwise controlled, this voltage increase will rapidly exceed the operating limitations of switching transistor 14 and energy storage capacitor 56 and result in serious damage to the power supply circuit.

In order to solve this circuit design problem, the FIG. 1 circuit incorporates an overvoltage protection circuit which includes output voltage sensing means consisting of series coupled semiconductor means 72 and biasing means 74.

Semiconductor means 72 in the preferred embodiment of the invention takes the form of two series coupled sidacs 76 and 78. Sidac 76 is coupled to voltage conductor 70 by voltage scaling means with a one to one voltage ratio in the form of a direct electrical connection. The specific sidacs selected for use in the FIG. 1 circuit each have a one hundred and thirty volt breakover voltage. As illustrated in FIG. 5A, the current flow through a sidac semiconductor device remains at a near-zero level until the sidac voltage reaches the breakover voltage. At the breakover voltage, the sidac transitions from a normal resistive mode of operation into a negative resistance mode of operation designated the foldback region in FIG. 5A. Operation within the foldback region begins at a first point defined by the breakover voltage and terminates at a second point defined by a lower operating limit voltage.

In the preferred embodiment of the FIG. 1 converter, the overvoltage protection circuit is designed to limit the maximum output voltage to two hundred and sixty volts. As the voltage level on voltage conductor 70 begins to exceed two hundred and sixty volts, sidacs 76 and 78 are operating at their breakover voltage where they begin to conduct current and enter the negative resistance foldback region. The flow of current through sidacs 76 sand 78 is transmitted to resistive biasing means 74 which results in the generating of an overvoltage signal which is coupled to the base of base drive shunt transistor 24 of the power supply disabling means. This overvoltage signal activated transistor 24 and shunts all base drive current away from switching transistor 14 to ground and causes switching transistor 14 to transition from the conductive state into the non-conductive state. With switching transistor 14 in the non-conductive state, the power supply output voltage on voltage conductor 70 ramps downward for a period of time. After a comparatively short but measurable time, the voltage impressed across sidacs 76 and 78 drops to a level below the lowest voltage capable of maintaining the sidacs in the foldback region defined by the second point of the foldback region and referred to as the lower operating limit voltage. At the lower operating limit voltage, the series-connected sidacs transition from operation in their negative resistance foldback region into the normal resistive mode of operation. When this transition occurs, the flow of current through sidacs 76 and 78 terminates, resulting in the removal of the overvoltage signal from the base of transistor 24. Base drive current is once again directed to the base terminal of switching transistor 14, causing it to resume normal operation.

If the circuit defect which initially activated the overvoltage protection circuit has not been cured, the resumed converter operation will once again begin increasing the voltage on energy storage capacitor 56. When the maximum desired output voltage is achieved on voltage conductor 70, the overvoltage protection circuit is activated once again. This cycle of activating, deactivating and reactivating the overvoltage protection circuit causes the output voltage on voltage conductor 70 to fluctuate from the maximum desired output voltage to a voltage level somewhat below that level until the circuit fault is ultimately cured. Because this circuit prevents overvoltage conditions, circuit defects of the type discussed above cannot damage any elements of the FIG. 1 power supply circuit.

A zener diode which completely breaks down and commences full current conduction at a predetermined breakdown voltage cannot successfully be used as a substitute for the semiconductor means of the present overvoltage protection circuit. Substituting a zener diode for sidacs 76 and 78 would merely result in circuit oscillation about the maximum desired output voltage and would not serve the purposes of the present invention.

Referring now to 5B, the voltage versus current plot of a related semiconductor device designated a disc is illustrated. Although sidacs are preferred over discs, a diac possesses the required breakover voltage/foldback region characteristics necessary for proper operation of the overvoltage protection circuit of the present invention.

FIG. 5C illustrates the voltage versus current characteristics of another semiconductor device referred to as a silicon bilateral switch (SBS) which also possesses a breakover voltage/foldback region characteristic of the type necessary for proper operation of the overvoltage protection circuit of the present invention. Semiconductor means in the form of a sidac is strongly preferred over either the diac or SBS alternatives discussed above.

Although one terminal of sidac 76 is shown directly coupled to voltage conductor 70, that specific type of circuit configuration is not necessary for proper operation of the overvoltage protection circuit. As would be immediately recognized by a person of ordinary skill in the art, a voltage scaling network or voltage divider network could be coupled across voltage conductor 70 and ground to scale the input voltage to a sidac to thereby render a sidac having a fixed breakover voltage rating capable of functioning to activate the overvoltage protection circuit at converter output voltages substantially different than the sidac breakover voltage. Although a pair of sidacs have been depicted as being coupled in series in FIG. 1, it would be readily apparent that single sidac may be used alone, that a variable number of sidacs could be coupled in series or that one or more sidacs could be used in connection with various voltage scaling means to cause an overvoltage protection circuit of the present invention to commence operation at any predetermined voltage.

FIG. 2 illustrates another configuration of variable impedance means 52 in the output circuit of the DC to DC converter illustrated in FIG. 1.

It will be apparent to those skilled in the art that the disclosed drive current regulator circuit, afterglow prevention circuit and overvoltage protection circuit for a DC to DC converter may be modified in numerous ways and may ssume many embodiments other than the preferred embodiments specifically set out and described above. For example, the FIG. 1 circuit has been discussed in connection with a twelve to forty-eight volts DC input voltage capacity although it is readily evident that the circuit elements could easily be modified to function normally with numerous other input voltage ranges. Accordingly, it is intended by the appended claims to cover all such modifications of the invention which fall within the true spirit and scope of the invention. 

I claim:
 1. An overvoltage protection circuit for limiting the output voltage of a power supply energizing a capacitive load to a maximum desired output voltage, comprising:a. output voltage sensing means includingi. semiconductor means having first and second terminals coupled to sense an applied voltage and including a resistive region of operation beginning at a breakover voltage and extending into a foldback region, said semiconductor means conducting a significant level of current while operating in the negative resistance foldback region for a defined time interval beginning as the applied voltage reaches the breakover voltage and ending as a lower operating limit voltage within the foldback region is reached where said semiconductor means transitions out of the negative resistance foldback region and resumes operation in the resisting region; ii. voltage scaling means for coupling the first terminal of said semiconductor means to sense the output voltage of said power supply and for scaling the output voltage such that the power supply voltage transmitted to the first terminal of said semiconductor means equals the breakover voltage of said semiconductor means when the output voltage of said power supply reaches the maximum desired output voltage; iii. biasing means having an input terminal coupled to the second terminal of said semiconductor means and an output terminal, said biasing means generating an overvoltage signal when said semiconductor means conducts current while operating in the foldback region and preventing operation of said semiconductor means in the negative resistance region beyond the foldback region; and b. power supply disabling means coupled to the second terminal of said biasing means and to said power supply and being responsive to the overvoltage signal from said biasing means for decreasing the power supply output voltage to a level below the maximum desired output voltage when said semiconductor means operates within the foldback region.
 2. The overvoltage protection circuit of claim 1 wherein said output voltage sensing means continues to generate the overvoltage signal until the power supply output voltage has been decreased to a predetermined level below the maximum desired output voltage.
 3. The overvoltage protection circuit of claim 2 wherein said biasing means discontinues generation of the overvoltage signal as said semiconductor means transitions from operation in the negative resistance foldback region to operation in the resistive region.
 4. The overvoltage protection circuit of claim 3 wherein said semiconductor means includes a sidac.
 5. The overvoltage protection circuit of claim 3 wherien said semiconductor means includes a diac.
 6. The overvoltage protection circuit of claim 3 wherein said semiconductor means includes a silicon bilateral switch.
 7. The overvoltage protection circuit of claim 4 wherein said biasing means inlcudes a resistor.
 8. The overvoltage protection circuit of claim 3 wherein said power supply further includes a switching transistor operating in response to a base drive current and wherein said power supply disabling means shunts the base drive current away from said switching transistor in response to the overvoltage signal.
 9. The overvoltage protection circuit of claim 8 wherein said semiconductor means includes a sidac.
 10. The overvoltage protection circuit of cliam 9 said sidac includes first and second terminals and wherein said voltage scaling means couples the first terminal of said sidac to directly sense the power supply output voltage.
 11. The overvoltage protection circuit of cliam 8 wherein said semiconductor means includes first and second sidacs coupled in series.
 12. The overvoltage protection circuit of claim 4 wherein said voltage scaling means includes a voltage conductor for couplng the first terminal of said sidac to directly sense the power supply output voltage.
 13. The overvoltage protection circuit of claim 1 wherein said power supply includes:a. a coupled inductor including a primary winding and a feedback winding; and b. a switching transistor having base, collector and emitter terminals and being coupled in series with said primary winding for switching between conductive and non-conductive states to control the flow of current through said primary winding.
 14. The overvoltage protection circuit of claim 13 wherein said disabling means includes means for switching the base terminal of said switching transistor to ground in response to the overvoltage signal to thereby switch said switching transistor out of the conductive state and into the non-conductive state.
 15. The overvoltage protection circuit of claim 14 wherein said disabling means further includes means for shunting current away from the base terminal of said switching transistor when the primary winding current reaches a predetermined valve to thereby switch said switching transistor out of the conductive state and into the non-conductive state.
 16. The overvoltage protection circuit of claim 14 wherein said capacitive load receives energy stored in said inductor after said switching transistor is switched into the non-conductive state by said shunting means.
 17. The overvoltage protection circuit of claim 16 wherein said semiconductor means includes a sidac. 